Academic project
SystemC Router Network Simulation
Academic router-network simulation with YAML configuration
- SystemC ·
- C++ ·
- CMake ·
- YAML ·
- Routing Simulation
Quick overview
Academic SystemC project simulating packet routing across configurable router networks, including CPU-to-memory transactions, multi-router topologies, YAML-driven configuration, routing policies, and TTL handling.
Project details are summarized to focus on architecture, implementation choices, and technical learning.
Context, responsibility, outcome, and takeaway
Context
Built as a university project for modeling an interconnection system where packets are routed through networks of SystemC routers, with both end-to-end CPU-to-memory behavior and focused verification executables.
My role
Implemented and documented the router simulation behavior, configuration flow, packet forwarding logic, topology setup, and verification scenarios across one-router and multi-router networks.
Result
Validated routing correctness, deterministic multi-hop propagation, configurable topology behavior, TTL-based packet dropping, and mixed CPU/MEM transactions across SystemC router networks.
Takeaway
Simulation work becomes easier to trust when topology, routing, observability, and safety behavior are all configurable and testable.
Configurable packet flow through router networks
01
CPU
02
Router network
03
Routing rules
04
Memory
05
Verification logs
Expandable details for the technical story
Why it matters
Although not a web/backend project, this work shows low-level engineering discipline: modeling system behavior, configuration-driven execution, routing correctness, verification scenarios, and debugging through deterministic logs.
Best signal
The strongest part of this project is not the technology itself, but the ability to define a configurable system, test multiple topologies, and validate behavior through repeatable simulation scenarios.
Core responsibilities and engineering details
- Packet model with source, destination, payload, and optional TTL fields
- Router data ports modeled with FIFO-based input/output behavior and configurable internal queues
- Routing tables mapping destinations to output ports
- Priority and round-robin arbitration policies
Additional technical details 6 more points
- YAML-driven configuration for routers, links, CPU attachments, memory attachments, queues, routes, and TTL behavior
- Configurator and ConfigBus flow for broadcasting router configuration messages
- CPU/MEM demo protocol using WR, RD, WR_ACK, and RD_RSP payloads
- Verification executables for 1-router, 8-router, 16-router, TTL, and diagram-based mixed CPU/MEM topologies
- Hop-by-hop test logs for observing packet propagation through multi-router links
- Safety timeouts and TTL drop behavior to avoid infinite packet forwarding